Description:
Job Title:DesignVerificationEngineerLocation:San Diego, CAExperience Level: 7+ YearsJob Description:We are seeking a skilledDesignVerificationEngineerwith strong expertise in System Verilog (SV) and UVM methodologies to join our team. The ideal candidate will have hands-on experience in developing, updating, and debuggingverificationtestbenches, with the ability to integrateVerificationIPs (VIPs) orDesignIPs into theverificationenvironment.Responsibilities:Develop, enhance, and debug System Veri
Jan 15, 2026;
from:
dice.com