Description:
"Exciting Opportunity! We're seeking a Low Power Principal Engineer/ASIC Engineer to join our team in San Diego, CA! Key Responsibilities: - Low power design and verification (UPF, VCLP) - Power analysis and optimization (PTPX) - STA and timing analysis - Synthesis and physical design (DC synthesis) Requirements: - 5+ years of experience in ASIC design, low power design, and verification - Proficiency in scripting languages (Shell, TCL, Perl, Python) - Experience with VCLP, PTPX, Formality,
May 7, 2025;
from:
dice.com