Description:
Pre-Layout Synthesis and STA Engineer Key Responsibilities: 1. Perform pre-layout synthesis to optimize digital designs for area, power, and timing. 2. Conduct static timing analysis (STA) to ensure design meets timing constraints. 3. Analyze and resolve timing issues, optimizing design for performance and power. 4. Collaborate with cross-functional teams to ensure design meets requirements. Requirements: 1. Education: Bachelor's/Master's degree in Electrical Engineering, Computer Engineering, o
May 6, 2025;
from:
dice.com