Description:
Vendor referrals and C2C will not be considered. Project, main deliverables: Support FPGA debug, simulation and test activities for existing platforms for defined features/escalations Create updated RTL design for identified issues and block level sims utilizing UVMF Support test case generation for UVMF Support mono, functional & SW integration through customer delivery Documentation updates/generation Hard Skills: Required (with demonstrated professional experience): Writing & Updating VHDL RT
Mar 14, 2025;
from:
dice.com